1. Technical Field
The present invention relates to an integrated circuit (IC), and more particularly, to an IC that has a memory cell array capable of simultaneously performing a data read operation and a data write operation.
2. Discussion of the Related Art
General synchronous random access memories (SRAMs) can transmit either read data or write data during each period of a clock signal. A double data rate (DDR) RAM increases a data transmission rate of an SRAM by transmitting data at both a rising edge and a falling edge of a clock signal. However, in a conventional memory device such as an SRAM, data input and output are performed via one input and output (I/O) pin. When using a common I/O pin, data that is input and output cannot be independently controlled. Thus, input and output frequencies of the data (e.g., bandwidth) are limited.
As the bandwidth of memory devices becomes important, memory devices using separate I/Os have been manufactured. In such memory devices, an input pin and an output pin are positioned separately on the memory device so data that is input and output can be independently controlled. A memory device that has separate input and output pins can receive, for example, a read command, a read address, a write command, a write address, and can write data within one period of a clock signal, thus increasing its operating frequency.
However, when a memory device having separate I/Os receives a read command, a read address, a write command, a write address, and writes data within one period of a clock signal, memory cell accesses are performed twice, resulting in a data read operation and a data write operation being performed within one period of a clock signal. Thus, because the activation of a word line for data reading and writing is performed twice within one period of a clock signal, the clock frequency is limited by the activation time of a word line.
FIG. 1 is a timing diagram illustrating an operation of a memory device having separate I/Os. Because the relationship between an address and a word line or the latency of input and output data vary according to the structure of the memory device, such a relationship or latency is not discussed.
Referring to FIG. 1, a write address WADD and a read address RADD are input within one period of a clock signal CLK. Addresses A0, A2, A4, and A6 input at a rising edge of the clock signal CLK are read addresses RADDs, and addresses A1, A3, A5, and A7 input at a falling edge of the clock signal CLK are write addresses WADDs. A read selection signal RES is used to select the read addresses RADDs, and a write selection signal WES is used to select the write address WADDs, respectively. A word line WL having a word line pulse AWLO for data reading and a word line pulse AWL1 for data writing is activated within one period of the clock signal CLK. Thus, one period of the clock signal CLK cannot be shorter than the activation time of the word line WL.